RRAM Characterization Analysis Notebook

This notebook contains Python analyses of data collected on the 256x256 (64K) TCAM array developed at Stanford. The TCAM has 4 WLs that are addressed by a single WL addr, and 2 BLs that are addressed by a single SL addr.

Notebook setup

Calibration

Read voltage sweep

Here, we sweep the READ voltage across different programmed conductances and measure average current to see how "linear" the RRAM is. At all conductances tested, the I-V curves appear to be very linear. This ohmic behavior may simplify sense amplifier design and improve accuracy.

We will operate at 0.2V READ voltage during the remainder of these experiments, but this data confirms that the resistances/conductances measured will look similar at other READ voltages.

FORMing

Load log file

The log file contains all the data from the dynamic FORM process. We need to parse it and look at some statistical properties of the FORMing process.

In this dataset, FORMing is done by dynamically incrementing VWL by 50mV starting from 1.3V until the cell resistance falls below 10kOhm. The VBL is fixed at 3.3V and the pulse width is 1ms.

FORMing VWL Distribution

As shown by the distribution, most cells FORM with a single pulse as indicated by the large bar at 1.3V (first pulse). The rest of the cells appear to FORM in a manner that looks like the right half of a Gaussian distribution.

FORMing Conductance Distribution

FORMing VWL Spatial Distribution

There seems to be a pattern in the FORMing voltages, repeating every 8 columns. This is probably a layout-dependent effect, as there is segmentation in the wordlines. The FORMing voltage appears to be lower at the edges.

FORMing Conductance Distribution

From the FORMing conductance distribution, we can infer that it is more difficult to bring the darker stripes of cells below 10kOhm, so the VWL is higher for those cells accordingly.

Multi-Bit Capability Evaluation

The first multi-bit test examines the post-programmed readout of 32 levels induced across the first 1024 cells of the array (32 cells/level * 32 levels). The programming method is DD-ISPP (dual-direction incremental step pulse programming), where the word line voltage is incremented until the cells fall into the target range. The main finding was that only the first bit line of the TCAM supports good multi-bit programming while the second bit line has huge relaxation problems. This may have something to do with the TCAM peripherals causing write disturbance. The data that led to this conclusion is presented below. All measurements are taken 15-30 minutes after programming. More information on the time-dependence of the distributions is given in the Retention section.

Note that every second cell (corresponding to the second bitline) above looks like it has deviated significantly from its programmed value. Next, we examine only cells on the first bitline to remove these outliers.

Now, we can try to pick out non-overlapping levels and examine them more carefully. We can get 5 non-overlapping levels here.

Let's examine the distributions with more data now (16378 cells):

If we filter down to 5 levels:

If we filter down to 4 levels:

Retention and Read Noise

In this section, we evaluate how well the cells can maintain their conductance values after programming. We first program 1024 cells (using the first bitline). After each cell is programmed, we immediately measure the short-term relaxation by performing 1000 READs. After all cells are programmed, we measure the long-term relaxation by continuously reading all cells.

Room-Temperature Retention/Read Noise

Let's look at the 5 levels we were considering before.

Example 1:

Example 2:

Example 3:

The conclusion is that READ noise and drift may become an issue when you place levels too close together. If we remove the second (orange) level, we have 2 bits per cell and the READ noise does not appear to pose an issue after 7 hours.

Room-Temperature READ Distribution after ~7hrs

Conductance Deviation vs. Initial Conductance

A good way to understand the stability of each conductance level is to look at the conductance deviation plot shown below. Intermediate conductances are less stable.

Average Absolute Conductance Deviation vs. Time

Average conductance deviation vs. time seems to increase in a power-law fashion. There seems to be a difference in the exponent based on the conductance level. Intermediate conductances deviate the fastest.

High-Temperature Retention

To perform high-temperature retention measurements, the chips were programmed and measured, then placed on a hot plate for 1 hour. After 1 hour, the chip was remeasured. The results are presented at three temperatures below.

One interesting observation is that the pre-bake distributions keep getting worse and worse. This means that the post-programmed relaxation is somehow affected by the baking. TODO: do retention/relaxation/noise measurements after baking

85C for 1hr

At 85C, there appears to be little effect of the baking on the resistance distributions.

110C for 1hr

At 110C, there appears to be little effect of the baking on the resistance distributions.

130C for 1hr

At 130C, there appears to be little new effect of the baking on the resistance distributions.

Average deviation from programmed value vs. temperature after 1hr

This indicates that there is little impact of baking on the chip. Possibly, electrical pulses are required during the heating for there to be an effect. Or the hot plate baking method may not be the right approach.

Endurance

To measure endurance, we perform SET/RESET cycling using a hardware-timed pulse train without READing (fast mode). The pulse train waveform is verified with the oscilloscope. We also validate with a software-timed pulse train (slow mode), which generally exhibits good agreement with the hardware-timed pulse train. We test different SET conditions at 1us and 20ns. We are basically unable to get the cells to fail in a reasonable amount of testing time.

Sweeps

TODO

Programming Methods and Tuning

Here, we evaluate various write-verify programming methods. In particular, we test out FPPV, ISPP, DD-ISPP,Smart-ISPP, Smart-DD-ISPP, GSR, and RADAR. Each algorithm uses fixed pulse width and assumes block RESET operation is available (GSR and (Smart)-DD-ISPP methods do not need block RESET). The algorithms are described below and each has tradeoffs in terms of:

  1. Number of tunable parameters: fewer means that the parameter tuning process is more straightforward and less time-consuming to configure, but greater number of parameters typically leads to lower pulse count
  2. Dynamic range of WL/BL/SL voltages: having fewer voltage levels to apply simplifies peripheral design in the array
  3. Number of pulses required: having fewer is always better, but usually requires more parameters to tune
  4. Difficulty of implementation: simpler algorithms require less control logic
Tunable Parameters per Level Difficulty of Implementation Dynamic Range Required Pulse Count (Estimate)
FPPV 1 1 1 5
ISPP 1 1 2 5
DD-ISPP 2 2 2 4
Smart-ISPP 2 2 2 3
Smart-DD-ISPP 3 3 2 2
RADAR 5 4 3 1
GSR 8 3 3 2

The tradeoffs for each algorithm will be described further below in the corresponding section.

TODO

FPPV

FPPV stands for Fixed Pulse Programming Voltage method, and as its name suggests, it involves the use of fixed amplitude pulses to program a cell to a given range. In terms of dynamic range: there is one BL level (for SET) and one SL level (for RESET). For WL voltage, there is one level for each targeted programming range. Hence, for targeting of N programming ranges, only N DAC levels are necessary for the WL, which is advantageous in terms of area (and potentially power) when designing peripheral memory circuits.

The idea of the algorithm is that when targeting a range i, you apply a pulse with the WL voltage that gets you there the fastest. As long as your conductance is lower than the target, you keep applying SET pulses with the corresponding amplitude, and when the conductance goes above the target, you use a strong RESET pulse to get back to HRS and try again.

FPPV is relatively easy to tune; first, you perform a sweep to determine how the WL voltage affects the final conductance, then you pick the WL voltages that result in the desired conductance range being achieved in minimum number of pulses.

TODO: make fppv_tune.py

ISPP

ISPP stands for Incremental Step Pulse Programming method, and as its name suggests, it involves the use of increasing (WL voltage) amplitude pulses to program a cell to a given range. In terms of dynamic range: there is one BL level (for SET) and one SL level (for RESET). For WL voltage, there is typically a larger degree of tunability required, and hence a higher resolution DAC will need to be used than for FPPV.

The idea of the algorithm is that when targeting a range i, you start from VWL = 0V and keep stepping up the WL voltage until you get to the target. As long as your conductance is lower than the target, you keep applying SET pulses with the corresponding amplitude, and when the conductance goes above the target, you use a strong RESET pulse to get back to HRS and try again.

ISPP is very easy to tune; there is only one parameter, the step size. To tune it, you can thus simply evaluate the algorithm with different step sizes.

TODO: make ispp_tune.py